This relates generally to integrated circuits and more particularly, to integrated circuits with flip-flops.
Integrated circuits often include communications circuitry such as transceiver circuitry. The transceiver circuitry sometimes includes flip-flops connected in a chain. The flip-flops are controlled by a single clock signal. Data is transferred from one flip-flop in the chain to a successive flip-flop in the chain as the clock signal oscillates.
A pair of consecutive flip-flops in the chain may include a positive edge-triggered flip-flop and a negative edge-triggered flip-flop. For example, consider a scenario in which a first positive edge-triggered flip-flop and a second negative edge-triggered flip-flop are connected in series. The first flip-flop has a first data input, a first data output, and a first clock input, whereas the second flip-flop has a second data input, a second data output, and a second clock input. The first data input receives data signals. The first data output is connected to the second data input. The first and second clock inputs receive a clock signal.
When the clock signal rises from low to high, data at the first data input is transferred to the first data output after a clock-to-output delay. When the clock signal falls from high to low, data at the second data input may be transferred to the second data output after a clock-to-output delay (i.e., data at the second data input may be latched by the second flip-flop).
As the data rate for transceiver circuitry increases, the clock period decreases. For data rates greater than 20 Gbps (as an example), the clock-to-output delay may take up a significant portion of the clock period (i.e., the clock-to-output delay may be greater than a quarter clock cycle). In such scenarios, variations such as process, voltage, and temperature variations, power supply noise, device mismatch, and other sources of variations may cause the second flip-flop to latch incorrect data.
It would therefore be desirable to be able to provide improved flip-flop circuitry that can properly latch desired data in the presence of variations.